The race and hazard in the sequential logic circuit is quite essential and must be considered when designing logic circuit. 时序逻辑电路中的竞争冒险是电路设计中必须考虑到的重要方面。
The method of judge and remove in the phenomenon of race and hazard of the combinational logic circuit 组合逻辑电路中的竞争冒险现象的判断和消除
A Descriptive Method of Race and Hazard in Logic Circuits 逻辑电路中竞争与冒险现象的一种描述
This paper proposes a complete algebraic analysis of detecting and eliminating race hazard after considering the existence of the third term. 作者考虑了该第三项的存在并给出了有关竞争冒险的完整代数分析。
The design of reflected binary counters without race hazard is described and is verified by experiment. 文中给出了反射二进制(格雷码)计数器的实用电路及设计要点。实验表明,这种计数器不存在竞争冒险。
Test circuit, test method and results of race hazard circuit are presented in this paper. 本文给出竞争冒险的测试电路、测试方法和测试结果。
Based on the experience from practice, this paper introduces the simple application of PLD in inertial guidance test system, it tables some proposal for race-hazard and recommend VHDL briefly. 本文根据实践中应用PLD的体会,介绍PLD在惯导测试系统中的简单应用,针对竞争-冒险问题提出一些建议,并对VHDL略做介绍。
The simplified algorithm for the functional expressions of elements speeds the simulation operation greatly and deals with the race, hazard, and oscillation problems in the asynchronous circuits effectively. 该系统中,对元件的功能表达式采用了较有效的化简算法,使模拟运算的速度大为提高。
After introducing the model of level asynchronous sequential circuit and the special hazard about race and hazard, it brings forward analysis way and solution to essential hazard about level asynchronous sequential circuit. 在介绍了电平异步时序逻辑电路的模型,电平异步时序电路的竞争冒险的特有的本质险象后,提出了电平异步时序电路的本质险象的分析判断方法和解决方案。
The problem of race hazard in CMOS circuits and its solution CMOS电路中的竞争冒险及其克服
Analysis on Race and Hazard of Digital Logic Circuits 数字逻辑电路的竞争与险象分析
Forming Secret of the Race Hazard Based on Experiment Method 基于实验方法揭示竞争冒险的成因奥秘
The concept, judge ways, overcomes and simulation of the race and hazard phenomenon in combination logic circuit are analyzed; 分析组合电路中的竞争冒险现象的概念、判断方法、克服与仿真;
The Design and Test of Race Hazard Experiment Circuit 竞争冒险实验电路的设计与测试